Methods and apparatus for an operational amplifier with a variable gain-bandwidth product

ABSTRACT

Various embodiments of the present technology comprise a method and apparatus for an operational amplifier with a variable gain-bandwidth product. According to various embodiments, an amplifier circuit comprising the operational amplifier operates in multiple stages and provides a low gain-bandwidth and a high gain-bandwidth.

BACKGROUND OF THE TECHNOLOGY

Many electrical systems utilize multiple operational amplifiers toperform different amplifying stages. However, a single,fully-differential amplifier that operates in multiple stages to providea desired output signal may be impacted by a load from a previous stage.For example, if the load on a second stage is larger than the load on afirst stage, then the operating frequency of the operational amplifiermust be increased during the second stage. When the operationalamplifier returns back to the first stage, increased thermal noise maybe observed as a result of the higher operating frequency during thefirst stage. In general, thermal noise has a negative impact on thesignal, resulting in a signal with less desirable signal-to-noisecharacteristics.

SUMMARY OF THE INVENTION

Various embodiments of the present technology comprise a method andapparatus for an operational amplifier with a variable gain-bandwidthproduct. According to various embodiments, an amplifier circuitcomprising the operational amplifier operates in multiple stages andprovides a low gain-bandwidth and a high gain-bandwidth.

BRIEF DESCRIPTION OF THE DRAWING FIGURES

A more complete understanding of the present technology may be derivedby referring to the detailed description when considered in connectionwith the following illustrative figures. In the following figures, likereference numbers refer to similar elements and steps throughout thefigures.

FIG. 1 is a block diagram of a sensor system comprising a multi-stageamplifier circuit in accordance with an exemplary embodiment of thepresent technology;

FIG. 2 is a circuit diagram of the multi-stage amplifier circuit duringa first reset stage in accordance with an exemplary embodiment of thepresent technology;

FIG. 3 is a circuit diagram of the multi-stage amplifier circuit duringa first fully-differential operating stage in accordance with anexemplary embodiment of the present technology;

FIG. 4 is a circuit diagram of the multi-stage amplifier circuit duringa second reset stage in accordance with an exemplary embodiment of thepresent technology;

FIG. 5 is a circuit diagram of the multi-stage amplifier circuit duringa second fully-differential operating stage in accordance with anexemplary embodiment of the present technology;

FIG. 6 is a circuit diagram of the multi-stage amplifier circuit duringa third reset stage in accordance with an exemplary embodiment of thepresent technology;

FIG. 7 is a circuit diagram of the multi-stage amplifier circuit duringa single-ended operating stage in accordance with an exemplaryembodiment of the present technology;

FIG. 8 is a timing diagram for operating the amplifier circuit inaccordance with an exemplary embodiment of the present technology;

FIG. 9 is a circuit diagram for a switching circuit in accordance withthe present technology;

FIG. 10 illustrates various gain-bandwidths as a function of frequencyin accordance with an exemplary embodiment of the present technology;

FIG. 11 is a circuit diagram of a first embodiment of an operationalamplifier in accordance with the present technology;

FIG. 12 is a circuit diagram of a second embodiment of an operationalamplifier in accordance with the present technology; and

FIG. 13 is a circuit diagram of a third embodiment of an operationalamplifier in accordance with the present technology.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

The present technology may be described in terms of functional blockcomponents and various processing steps. Such functional blocks may berealized by any number of components configured to perform the specifiedfunctions and achieve the various results. For example, the presenttechnology may employ various sensors, analog-to-digital converters,switch elements, logic circuits, signal generators, and the like, whichmay carry out a variety of functions. In addition, the presenttechnology may be practiced in conjunction with any number of electronicsystems, such as sensor systems or any other systems that require afully-differential mode and a single-ended mode and/or an operationalamplifier with a variable gain-bandwidth, and the systems described aremerely exemplary applications for the technology.

Methods and apparatus for an operational amplifier with a variablegain-bandwidth product according to various aspects of the presenttechnology may operate in conjunction with any suitable sensor, such asan image sensor or a gyro sensor, and any suitable analog-to-digitalconverter. Referring to FIG. 1, an exemplary sensor system 100 maycomprise a sensor circuit 105, an amplifier circuit 110, and ananalog-to-digital converter (ADC) 115 that operate together to amplifysensor signals and convert analog sensor signals into digital signals.

The sensor circuit 105 may generate various sensor signals. In somecases, it may be desired to amplify the sensor signals prior toprocessing the signals. For example, the sensor circuit 105 may comprisean image sensor for generating pixel signals.

The amplifier circuit 110 may be configured to receive and amplify thesensor signals. According to an exemplary embodiment, and referring toFIG. 2 the amplifier circuit 110 may comprise a plurality of switches,such as switches SW1A:SW12A and switches SW1B:SW12B, an operationalamplifier (op-amp) 200, and a switching circuit 205.

According to various embodiments, the op-amp 200 may be configured asboth a single-ended op-amp and a fully-differential op-amp. Accordingly,the op-amp 200 is capable of operating in both the single-ended mode andthe fully-differential mode. For example, the op-amp 200 may beconfigured to receive and respond to a mode signal, such as a high modesignal ‘H’ (i.e., a high voltage) and a low mode signal ‘L’ (i.e., a lowvoltage).

Referring to FIG. 11, in a first embodiment, the op-amp 200(1) maycomprise a plurality of sub-circuits, such as a first sub-circuit 220, asecond sub-circuit 225, a third sub-circuit 230, and a fourthsub-circuit 235, that are connected together and configured to amplifyan input signal, such as a first input signal V_(IM) and a second inputsignal V_(IP).

The first, third, and fourth sub-circuits 220, 230, 235 may be directlyconnected to each other via a bias node B_(COM) and the secondsub-circuit 225 may be connected directly to the first and thirdsub-circuits 220, 230. The op-amp 200(1) may further comprise aplurality of mode switch elements, such as a first mode switch 245 and asecond mode switch 260, that are selectively enabled/disabled to operatethe op-amp 200(1) in one of the fully-differential mode or thesingle-ended mode at any given time.

The first sub-circuit 220 may comprise a first plurality of transistors,such as a first transistor M1, a second transistor M2, a thirdtransistor M3, and a fourth transistor M4. The first and secondtransistors M1, M2 may be connected in series. The first and secondtransistors M1, M2 may comprise p-channel transistors. A source terminalof the first transistor M1 may be connected to a supply voltage VDD anda drain terminal of the second transistor M2 may be connected to a firstoutput node N_(OUT1). Gate terminals of each of the first and secondtransistors M1, M2 may be connected to a bias voltage.

The third and fourth transistors M3, M4 may be connected in series. Thethird and fourth transistors M3, M4 may comprise n-channel transistors.A drain terminal of the third transistor M3 may be connected to thefirst output node N_(OUT1) and a source terminal of the fourthtransistor M4 may be connected to a reference voltage, such as a ground.A gate terminal of the third transistor M3 may be connected to a biasvoltage and a gate terminal of the fourth transistor may be connected tothe bias node B_(COM). The first output node N_(OUT1) may also serve asa first output terminal for a first output voltage V_(OUTM).

The first mode switch 245 may comprise a transistor, such as ann-channel transistor. A drain terminal of the first mode switch 245 maybe connected to the first output node N_(OUT1), a source terminal of thefirst mode switch 245 may be connected to the bias node B_(COM), and agate terminal of the first mode switch 245 may be configured to receivethe mode signal.

The second sub-circuit 225 may comprise a second plurality oftransistors, such as a fifth transistor M5, a sixth transistor M6, and aseventh transistor M7. The fifth transistor M5 may comprise a p-channeltransistor comprising a source terminal connected to the supply voltageVDD and a drain terminal connected to the sixth and seventh transistorsM6, M7. A gate terminal of the fifth transistor M5 may be connected to abias voltage.

The sixth and seventh transistor M6, M7 may be connected in parallelwith each other and in series with the fifth transistor M5. The sixthand seventh transistors M6, M7 may comprise p-channel transistors.Accordingly, source terminals of the sixth and seventh transistors M6,M7 may each be connected to the drain terminal of the fifth transistorM5. A gate terminal of the sixth transistor M6 may be connected to thefirst input voltage V_(IP) and a gate terminal of the seventh transistorM7 may be connected to the second input voltage V_(IM). A drain terminalof the sixth transistor M6 may be directly connected to the firstsub-circuit 220, for example to the source terminal of the thirdtransistor M3 and the drain terminal of the fourth transistor M4. Adrain terminal of the seventh transistor M7 may be directly connected tothe third sub-circuit 230.

The third sub-circuit 230 may comprise a third plurality of transistors,such as an eighth transistor M8, a ninth transistor M9, a tenthtransistor M10, and an eleventh transistor M11. The eighth and ninthtransistors M8, M9 may be connected in series. The eighth and ninthtransistors M8, M9 may comprise p-channel transistors. A source terminalof the eighth transistor M8 may be connected to the supply voltage VDDand a drain terminal of the ninth transistor M9 may be connected to asecond output node N_(OUT2). Gate terminals of each of the eighth andninth transistors M8, M9 may be connected to a bias voltage.

The tenth and eleventh transistors M10, M11 may be connected in series.The tenth and eleventh transistors M10, M11 may comprise n-channeltransistors. A drain terminal of the tenth transistor M10 may beconnected to the second output node N_(OUT2) and a source terminal ofthe eleventh transistor M11 may be connected to a reference voltage,such as the ground. A gate terminal of the tenth transistor M10 may beconnected to a bias voltage and a gate terminal of the eleventhtransistor M11 may be connected to the bias node B_(COM). The secondoutput node N_(OUT2) may also serve as a second output terminal for asecond output voltage V_(OUTP).

The op-amp 200(1) may further comprise a dummy switch 255 to improve theaccuracy of an output of the op-amp 200(1). The dummy switch 255 maycomprise a transistor, such as an n-channel transistor. According to thepresent embodiment, the dummy switch 255 is always set to OFF (open) forall operations.

The fourth sub-circuit 235 may comprise a fourth plurality oftransistors, such as a twelfth transistor M12, a thirteenth transistorM13, and a fourteenth transistor M14. The twelfth transistor M12 maycomprise a p-channel transistor comprising a source terminal connectedto the supply voltage VDD and a drain terminal connected to thethirteenth and fourteenth transistors M13, M14. A gate terminal of thetwelfth transistor M12 may be connected to a bias voltage.

The thirteenth and fourteenth transistors M13, M14 may be connected inparallel with each other and in series with the twelfth transistor M12.The thirteenth and fourteenth transistors M13, M14 may comprisep-channel transistors. Accordingly, source terminals of the thirteenthand fourteenth transistors M13, M14 may each be connected to the drainterminal of the twelfth transistor M12. A gate terminal of thethirteenth transistor M13 may be connected to a common voltage VCOM anda gate terminal of the fourteenth transistor M14 may be connected to acommon mode feedback signal CMFB.

The fourth sub-circuit 235 may further comprise a fifteenth transistorM15 and a sixteenth transistor M16 arranged as a current mirror andconnected to the thirteenth and fourteenth transistors M13, M14. Thefifteenth and sixteenth transistors M15, M16 may comprise n-channeltransistors. Accordingly, a drain terminal of the fifteenth transistorM15 may be connected to a drain terminal of the thirteenth transistorM13 and a drain terminal of the sixteenth transistor M16 may beconnected to the a drain terminal of the fourteenth transistor M14. Thedrain terminal of the sixteenth transistor M16 may also be connected toa gate terminal of the fifteenth transistor M15 and a gate terminal ofthe sixteenth transistor M16.

The second mode switch 260 may comprise a transistor, such as ann-channel transistor. A drain terminal of the second mode switch 260 maybe connected to the fourth sub-circuit 235, a source terminal of thesecond mode switch 260 may be connected to the bias node B_(COM), and agate terminal of the second mode switch 260 may be configured to receivethe mode signal.

Referring to FIG. 12, in a second embodiment, the op-amp 200(2) may beconfigured to operate in both a fully-differential mode and asingle-ended mode. For example, the op-amp 200(2) may be configured toreceive and respond to a mode signal, such as a high mode signal ‘H’(i.e., a high voltage) and a low mode signal ‘L’ (i.e., a low voltage).According to the present embodiment, the op-amp 200(2) may comprise aplurality of sub-circuits, such as a first sub-circuit 920, a secondsub-circuit 925, a third sub-circuit 930, and a fourth sub-circuit 935,that are connected together and configured to amplify an input signal,such as a first input signal V_(IP) and a second input signal V_(IM).For example, the first, third, and fourth sub-circuits 920, 930, 935 maybe directly connected to each other via a bias node B_(COM) and thesecond sub-circuit 925 may be connected directly to the first and thirdsub-circuits 920, 930. The op-amp 200(2) may further comprise aplurality of mode switch elements, such as a first mode switch 905 and asecond mode switch 910, that are selectively enabled/disabled to operatethe op-amp 200(2) in one of the fully-differential mode or thesingle-ended mode at any given time.

The first sub-circuit 920 may comprise a first plurality of transistors,such as a first transistor M1, a second transistor M2, a thirdtransistor M3, and a fourth transistor M4. The first and secondtransistors M1, M2 may be connected in series. The first and secondtransistors M1, M2 may comprise n-channel transistors. A source terminalof the first transistor M1 may be connected to a reference voltage, suchas a ground, and a drain terminal of the second transistor M2 may beconnected to a first output node N_(OUT1). Gate terminals of each of thefirst and second transistors M1, M2 may be connected to a bias voltage.

The third and fourth transistors M3, M4 may be connected in series. Thethird and fourth transistors M3, M4 may comprise p-channel transistors.A drain terminal of the third transistor M3 may be connected to thefirst output node N_(OUT1) and a source terminal of the fourthtransistor M4 may be connected to a supply voltage VDD. A gate terminalof the third transistor M3 may be connected to a bias voltage and a gateterminal of the fourth transistor may be connected to the bias nodeB_(COM). The first output node NOM may also serve as a first outputterminal for a first output voltage V_(OUTM).

The first mode switch 905 may comprise a transistor, such as a p-channeltransistor. A source terminal of the first mode switch 905 may beconnected to the bias node B_(COM), a drain terminal of the first modeswitch 905 may be connected to the first output node N_(OUT1), and agate terminal of the first mode switch 905 may be configured to receivethe mode signal.

The second sub-circuit 925 may comprise a second plurality oftransistors, such as a fifth transistor M5, a sixth transistor M6, and aseventh transistor M7. The fifth transistor M5 may comprise an n-channeltransistor with a source terminal connected to the reference voltage anda drain terminal connected to the sixth and seventh transistors M6, M7.A gate terminal of the fifth transistor may be connected to a biasvoltage.

The sixth and seventh transistor M6, M7 may be connected in parallelwith each other and in series with the fifth transistor M5. The sixthand seventh transistors M6, M7 may comprise n-channel transistors.Accordingly, source terminals of the sixth and seventh transistors M6,M7 may each be connected to the drain terminal of the fifth transistorM5. A gate terminal of the sixth transistor M6 may be connected to thefirst input voltage V_(IP) and a gate terminal of the seventh transistorM7 may be connected to the second input voltage V_(IM). A drain terminalof the sixth transistor M6 may be directly connected to the firstsub-circuit 920, for example to the source terminal of the thirdtransistor M3 and the drain terminal of the fourth transistor M4. Adrain terminal of the seventh transistor M7 may be directly connected tothe third sub-circuit 930.

The third sub-circuit 930 may comprise a third plurality of transistors,such as an eighth transistor M8, a ninth transistor M9, a tenthtransistor M10, and an eleventh transistor M11. The eighth and ninthtransistors M8, M9 may be connected in series. The eighth and ninthtransistors M8, M9 may comprise n-channel transistors. A source terminalof the eighth transistor M8 may be connected to the reference voltageand a drain terminal of the ninth transistor M9 may be connected to asecond output node N_(OUT2). Gate terminals of each of the eighth andninth transistors M8, M9 may be connected to a bias voltage.

The tenth and eleventh transistors M10, M11 may be connected in series.The tenth and eleventh transistors M10, M11 may comprise p-channeltransistors. A drain terminal of the tenth transistor M10 may beconnected to the second output node N_(OUT2) and a source terminal ofthe eleventh transistor M11 may be connected to the supply voltage VDD.A gate terminal of the tenth transistor M10 may be connected to a biasvoltage and a gate terminal of the eleventh transistor M11 may beconnected to the bias node B_(COM). The second output node N_(OUT2) mayalso serve as a second output terminal for a second output voltageV_(OUTP).

The op-amp 200(2) may further comprise a dummy switch 915 to improve theaccuracy of an output of the op-amp 200(2). The dummy switch 915 maycomprise a transistor, such as a p-channel transistor. According to thepresent embodiment, the dummy switch 915 is always set to OFF (open) forall operations.

The fourth sub-circuit 935 may comprise a fourth plurality oftransistors, such as a twelfth transistor M12, a thirteenth transistorM13, and a fourteenth transistor M14. The twelfth transistor M12 maycomprise an n-channel transistor with a source terminal connected to thereference voltage and a drain terminal connected to the thirteenth andfourteenth transistors M13, M14. A gate terminal of the twelfthtransistor M12 may be connected to a bias voltage.

The thirteenth and fourteenth transistors M13, M14 may be connected inparallel with each other and in series with the twelfth transistor M12.The thirteenth and fourteenth transistors M13, M14 may comprisen-channel transistors. Accordingly, source terminals of the thirteenthand fourteenth transistors M13, M14 may each be connected to the drainterminal of the twelfth transistor M12. A gate terminal of thethirteenth transistor M13 may be connected to a common voltage VCOM anda gate terminal of the fourteenth transistor M14 may be connected to acommon mode feedback signal CMFB.

The fourth sub-circuit 1035 may further comprise a fifteenth transistorM15 and a sixteenth transistor M16 arranged as a current mirror andconnected to the thirteenth and fourteenth transistors M13, M14. Thefifteenth and sixteenth transistors M15, M16 may comprise p-channeltransistors. Accordingly, a drain terminal of the fifteenth transistorM15 may be connected to a drain terminal of the thirteenth transistorM13 and a drain terminal of the sixteenth transistor M16 may beconnected to the a drain terminal of the fourteenth transistor M14. Thedrain terminal of the sixteenth transistor M16 may also be connected toa gate terminal of the fifteenth transistor M15 and a gate terminal ofthe sixteenth transistor M16.

The second mode switch 910 may comprise a transistor, such as ap-channel transistor. A drain terminal of the second mode switch 910 maybe connected to the fourth sub-circuit 935, a source terminal of thesecond mode switch 910 may be connected to the bias node B_(COM), and agate terminal of the second mode switch 910 may be configured to receivethe mode signal.

Referring to FIG. 13, in a third embodiment, the op-amp 200(3), may beconfigured to operate in both a fully-differential mode and asingle-ended mode. For example, the op-amp 200(3) may be configured toreceive and respond to a mode signal, such as a high mode signal ‘H’(i.e., a high voltage) and a low mode signal ‘L’ (i.e., a low voltage).According to the present embodiment, the op-amp 200(3) may comprise aplurality of sub-circuits, such as a first sub-circuit 1020, a secondsub-circuit 1025, a third sub-circuit 1030, and a fourth sub-circuit1035, which are connected together and configured to amplify an inputsignal, such as a first input signal VIP and a second input signal VIM.For example, the first, third, and fourth sub-circuits 1020, 1030, 1035may be directly connected to each other via a bias node B_(COM) and thesecond sub-circuit 1025 may be connected directly to the first and thirdsub-circuits 1020, 1030. The op-amp 200(3) may further comprise aplurality of mode switch elements, such as a first mode switch 1005 anda second mode switch 1010, that are selectively enabled/disabled tooperate the op-amp 200(3) in one of the fully-differential mode or thesingle-ended mode at any given time.

The first sub-circuit 1020 may comprise a first plurality oftransistors, such as a first transistor M1, a second transistor M2, athird transistor M3, and a fourth transistor M4. The first and secondtransistors M1, M2 may be connected in series. The first and secondtransistors M1, M2 may comprise p-channel transistors. A source terminalof the first transistor M1 may be connected to a supply voltage VDD anda drain terminal of the second transistor M2 may be connected to a firstoutput node N_(OUT1). Gate terminals of each of the first and secondtransistors M1, M2 may be connected to a bias voltage.

The third and fourth transistors M3, M4 may be connected in series. Thethird and fourth transistors M3, M4 may comprise n-channel transistors.A drain terminal of the third transistor M3 may be connected to thefirst output node N_(OUT1) and a source terminal of the fourthtransistor M4 may be connected to a reference voltage, such as a ground.A gate terminal of the third transistor M3 may be connected to a biasvoltage and a gate terminal of the fourth transistor M4 may be connectedto the bias node B_(COM). The first output node N_(OUT1) may also serveas a first output terminal for a first output voltage V_(OUTM).

The first mode switch 1005 may comprise a transistor, such as ann-channel transistor. A drain terminal of the first mode switch 1005 maybe connected to the first output node N_(OUT1), a source terminal of thefirst mode switch 1005 may be connected to the bias node B_(COM), and agate terminal of the first mode switch 1005 may be configured to receivethe mode signal.

The second sub-circuit 1025 may comprise a plurality of transistors,such as a fifth transistor M5, a sixth transistor M6, and a seventhtransistor M7. The fifth transistor M5 may comprise a p-channeltransistor comprising a source terminal connected to the supply voltageVDD and a drain terminal connected to the sixth and seventh transistorsM6, M7. A gate terminal of the fifth transistor M5 may be connected to abias voltage.

The sixth and seventh transistor M6, M7 may be connected in parallelwith each other and in series with the fifth transistor M5. The sixthand seventh transistors M6, M7 may comprise p-channel transistors.Accordingly, source terminals of the sixth and seventh transistors M6,M7 may each be connected to the drain terminal of the fifth transistorM5. A gate terminal of the sixth transistor M6 may be connected to thefirst input voltage V_(IP) and a gate terminal of the seventh transistorM7 may be connected to the second input voltage V_(IM). A sourceterminal of the sixth transistor M6 may be directly connected to thefirst sub-circuit 1020, for example to the source terminal of the thirdtransistor M3 and the drain terminal of the fourth transistor M4. Adrain terminal of the seventh transistor M7 may be directly connected tothe third sub-circuit 1030.

The second sub-circuit 1025 may further comprise an eight transistor M8,a ninth transistor M9, and a tenth transistor M10, wherein M8, M9 andM10 comprise n-channel transistors. A gate terminal of the eighttransistor M8 is connected to the first input voltage V_(IP) and a drainterminal is connected to the first sub-circuit 1020, for example betweenthe first and second transistors M1, M2. A gate terminal of the ninthtransistor M9 is connected to the second input voltage V_(IM) and adrain terminal is connected to the third sub-circuit 1030. Sourceterminals of the eighth and ninth transistors M8, M9 are connected to adrain terminal of tenth transistor M10. A source terminal of the tenthtransistor M10 may be connected to the reference voltage.

The third sub-circuit 1030 may comprise a third plurality oftransistors, such as an eleventh transistor M11, a twelfth transistorM12, a thirteenth transistor M13, and a fourteenth transistor M14. Theeleventh and twelfth transistors M11, M12 may be connected in series.The eleventh and twelfth transistors M11, M12 may comprise p-channeltransistors. A source terminal of the eleventh transistor M11 may beconnected to the supply voltage VDD and a drain terminal of the twelfthtransistor M12 may be connected to a second output node NOM. Gateterminals of each of the eleventh and twelfth transistors M11, M12 maybe connected to a bias voltage.

The thirteenth and fourteenth transistors M13, M14 may be connected inseries. The thirteenth and fourteenth transistors M13, M14 may comprisen-channel transistors. A drain terminal of the thirteenth transistor M13may be connected to the second output node NOM and a source terminal ofthe fourteenth transistor M14 may be connected to a reference voltage,such as the ground. A gate terminal of the thirteenth transistor M13 maybe connected to a bias voltage and a gate terminal of the fourteenthtransistor M14 may be connected to the bias node B_(COM). The secondoutput node NOM may also serve as a second output terminal for a secondoutput voltage V_(OUTP).

The op-amp 200(3) may further comprise a dummy switch 1015 to improvethe accuracy of an output of the op-amp 200(3). The dummy switch 1015may comprise a transistor, such as an n-channel transistor. According tothe present embodiment, the dummy switch 1015 is always set to OFF(open) for all operations.

The fourth sub-circuit 1035 may comprise a fourth plurality oftransistors, such as a fifteenth transistor M15, a sixteenth transistorM16, and a seventeenth transistor M17. The fifteenth transistor M15 maycomprise a p-channel transistor with a source terminal connected to thesupply voltage VDD and a drain terminal connected to the sixteenth andseventeenth transistors M16, M17. A gate terminal of the fifteenthtransistor M15 may be connected to a bias voltage.

The sixteenth and seventeenth transistors M16, M17 may be connected inparallel with each other and in series with the fifteenth transistorM15. The sixteenth and seventeenth transistors M16, M17 may comprisep-channel transistors. Accordingly, source terminals of the sixteenthand seventeenth transistors M16, M17 may each be connected to the drainterminal of the fifteenth transistor M15. A gate terminal of thesixteenth transistor M16 may be connected to a common voltage V_(COM)and a gate terminal of the seventeenth transistor M17 may be connectedto a common mode feedback signal CMFB.

The fourth sub-circuit 1035 may further comprise an eighteenthtransistor M18 and a nineteenth transistor M19 arranged as a currentmirror and connected to the sixteenth and seventeenth transistors M16,M17. The eighteenth and nineteenth transistors M18, M19 may comprisen-channel transistors. Accordingly, a drain terminal of the eighteenthtransistor M18 may be connected to a drain terminal of the sixteenthtransistor M16 and a drain terminal of the nineteenth transistor M19 maybe connected to the a drain terminal of the seventeenth transistor M17.The drain terminal of the nineteenth transistor M19 may also beconnected to a gate terminal of the eighteenth transistor M18 and a gateterminal of the nineteenth transistor M19.

The second mode switch 1010 may comprise a transistor, such as ann-channel transistor. A drain terminal of the second mode switch 1010may be connected to the fourth sub-circuit 1035, a source terminal ofthe second mode switch 1010 may be connected to the bias node B_(COM),and a gate terminal of the second mode switch 1010 may be configured toreceive the mode signal.

The sensor system 100 may further comprise a control circuit (not shown)configured to generate the mode signal (‘H’ and ‘L’) according to thedesired mode operation. For example, the control circuit may generatethe high mode signal (‘H’) to operate the op-amp 200 in the single-endedmode and may generate the low mode signal (‘L’) to operate the op-amp200 in the fully-differential mode. The control circuit may comprisevarious logic gates and/or other circuitry suitable for generating adigital signal. The control circuit may be further configured togenerate various switch signals (SW) to selectively operate theplurality of switches SW1A:SW12A and SW1B:SW12B (FIG. 2) through one ormore signal paths.

The control circuit may comprise or operate in conjunction with aninverter 200. The inverter 265 may be configured to receive the modesignal at an input terminal and output a signal having an oppositelogic-level. For example, when the inverter 265 receives a low modesignal ‘L’ (i.e., low voltage), it outputs a high mode signal (i.e.,high voltage), and when the inverter 200 receives a high mode signal, itoutputs a low mode signal. The inverter may comprise a logic gate, suchas a NOT gate, for implementing logical negation. Alternatively, theinverter 265 may be integrated within the op-amp 200 or the amplifiercircuit 110.

Referring to FIGS. 2 and 9, the switching circuit 205 may be configuredto selectively store charge and control a gain-bandwidth of the op-amp200. For example, the switching circuit 205 may be configured to operateaccording to a gain-bandwidth setting.

According to an exemplary embodiment, the switching circuit 205 maycomprise a first gain switch SW13 connected in series with a firstcharge storage device 210 (e.g., a capacitor or a transistor) and asecond gain switch SW15 connected in series with the first chargestorage device 210. The switching circuit 205 may further comprise athird gain switch SW14 connected in series with a second charge storagedevice 215 (e.g., a capacitor or a transistor) and a fourth gain switchSW16 connected in series with the second charge storage device 215. Theseries-connected circuits are connected in parallel with each other.

The switching circuit 205 may be further configured to have a variablecapacitance. For example, the first and second charge storage devices210, 215 may comprise a conventional capacitor with a variablecapacitance or a MOS (metal-oxide-semiconductor) transistor having agate capacitance. Due to their structure, MOS transistors have aparasitic capacitance that varies according to a voltage potentialacross the transistor. The parasitic capacitance may comprise gate-draincapacitance, a gate-source capacitance, and a drain-source capacitance,collectively referred to as the gate capacitance. Accordingly, the gatecapacitance of the switching circuit 205 may vary based on the first andsecond output voltages V_(OUTN), V_(OUTP).

The capacitance of the switching circuit 205 may have an effect on thegain-bandwidth and thermal noise V_(N) of the op-amp 200. For example,and referring to FIG. 10, when a capacitance of 6.0 pF (pico Farads) isprovided by the switching circuit 205, the gain-bandwidth of the op-amp200 is 1.2 MHz (B₁, gain-bandwidth at a higher capacitance). Incontrast, when the capacitance of the switching circuit 205 is zero, thegain-bandwidth of the op-amp 200 is 5.7 MHz (B₂, gain-bandwidth at alower capacitance). In general, the relationship between thegain-bandwidth and the thermal noise V_(N) is described according to thefollowing equation:

V_(N)=√{square root over (4kTRB)}, where k is Boltzmann's constant, T istemperature, R is a resistance, and B is the gain-bandwidth. When thegain-bandwidth decreases, the thermal noise is described according tothe following equation:

${V_{N} = {\sqrt{4\; k\; {{TR}\left( \frac{B}{N} \right)}} = \frac{\sqrt{4\; k\; {TRB}}}{\sqrt{N}}}},$

where N=B₂/B₁.

Accordingly, a decrease in the gain-bandwidth results in a decrease tothe thermal noise by a factor of

$\frac{1}{\sqrt{\frac{B_{2}}{B_{1}}}},$

where B₁ is the gain-bandwidth at a higher capacitance and B₂ is thegain-bandwidth at a lower capacitance than B₁.

According to an exemplary embodiment, the switching circuit 205 isconnected to the output terminals of the op-amp 200. For example, thefirst and third gain switches SW13, SW14 are directly connected to thesecond output terminal (V_(OUTP)) and the second and fourth gainswitches SW15, SW16 are directly connected to the first output terminal(V_(OUTN)). The first and third gain switches SW13, SW14 are alsodirectly connected to an input terminal of the ADC 115.

Each gain switch SW13:16 may operate according to a switch signal. Forexample, the system 100 may comprise a switch control circuit 900 togenerate various switch signals that operate various switches in thesystem 100. The switch control circuit 900 may be responsive to thegain-bandwidth setting. In other words, the switch control circuit 900generates the switch signals based on the gain-bandwidth setting. Forexample, when a high gain-bandwidth is desired, a first gain-bandwidthsetting may be used and when a low gain-bandwidth is desired, a secondgain-bandwidth setting may be used. When the high gain-bandwidth isdesired, the gain-bandwidth setting may turn OFF (open) all the gainswitches SW13:16. When the low gain-bandwidth is desired, thegain-bandwidth setting may turn ON (closed) all the gain switchesSW13:16, or alternatively may turn OFF the first and second gainswitches SW13, SW15 and turn ON the third and fourth gain switches SW14,SW16.

The ADC 115 may be configured to convert an analog signal into a digitalsignal. For example, the ADC 115 may be connected directly to the secondoutput terminal of the op-amp 200.

According to an exemplary embodiment, it may be desired to increase ordecrease the operating frequency of the op-amp 200. For example, it maybe desired to operate the op-amp 200 at a low frequency. This may beachieved by increasing the capacitance of the op-amp 200 via theswitching circuit 205, which has the effect of decreasing thegain-bandwidth of the op-amp 200. Accordingly, by selectively operatingthe gain switches SW13:16, the amplifier circuit 110 stores charge onthe first and second charge storage devices 210,215 which slows down theop-amp 200, narrows the bandwidth reduces the thermal noise.

In contrast, it may be desired to operate the op-amp 200 at a highfrequency.

This may be achieved by decreasing the capacitance of the op-amp 200 viathe switching circuit 205, which has the effect of increasing thegain-bandwidth of the op-amp 200. Accordingly, by selectively operatingthe gain switches SW13:16, no load is stored on the first and secondcharge storage devices 210, 215 and the bandwidth of the op-amp 200increases, which speeds up the op-amp 200 operation.

In an exemplary operation, and referring to FIGS. 2-8 and 11, theamplifier circuit 110 may enter a first reset state (RESET 1). Duringthe first reset state, switches SW1A,B, SW3A,B, SW5A,B, SW6A,B, SW8B,SW9A,B, and SW11A,B are ON; switches SW2A,B, SW4A,B, SW7, SW10A,B, andSW12A,B are OFF; the mode signal is set to low ‘L’, and the gainswitches SW13:16 are ON to increase the capacitance and decrease thegain-bandwidth of the op-amp 200.

During a first amplifying stage, which immediately follows the firstreset state, the op-amp 200 may operate in the fully-differential modewherein switches SW1A,B remain ON, switches SW2A,B remain OFF, switchesSW3A,B remain ON, switches SW4A,B remain OFF, switches SW5A,B remain ON,switches SW6A,B are turned OFF, switch SW7 remains OFF, switch SW8Bremains ON, switches SW9A,B remain ON, switches SW10A,B are turned ON,switches SW11A,B are turned OFF, switches SW12A,B remain OFF, switchesSW13:16 remain ON, and the mode signal remains low. Since capacitance isadded, via the switching circuit 205 during the first amplifying stage,the operating frequency of the op-amp 200 slows down, which in turn,results in less thermal noise in the output signals of the op-amp 200.

During a second reset state (RESET 2), which immediately follows thefirst amplifying stage, the mode signal remains low, switches SW1A,Bremain ON, switches SW2A,B remain OFF, switches SW3A,B remain ON,switches SW4A,B remain OFF, switches SW5A,B are turned OFF, switchesSW6A,B are turned ON, switch SW7 remains OFF, switch SW8B remains ON,switches SW9A,B is turned OFF, switches SW10A,B are turned OFF, switchesSW11A,B remain OFF, switches SW12A,B remain OFF, and the gain switchesSW13:16 are turned OFF to disconnect the capacitance of the switchingcircuit 205 from the op-amp 200 and increase the gain-bandwidth of theop-amp 200.

During a second amplifying stage, which immediately follows the secondreset state, the op-amp may operate in the fully-differential mode,wherein switches SW1A,B remain ON, switches SW2A,B are turned ON,switches SW3A,B are turned OFF, switches SW4A,B remain OFF, switchesSW5A,B remain OFF, switches SW6A,B are turned OFF, switch SW7 remainsOFF, switch SW8B remains ON, switches SW9A,B remain OFF, switchesSW10A,B remain OFF, switches SW11A,B are turned ON, switches SW12A,B areturned ON, and switches SW13:16 remain OFF. Since no additionalcapacitance is added, via the switching circuit 205 during the secondamplifying stage, the gain-bandwidth increases and the operatingfrequency of the op-amp 200 speeds up (increases).

During a third reset state (RESET 3), which immediately follows thesecond amplifying stage, the mode signal is set to high ‘H’, switchesSW1A,B are turned OFF, switches SW2A,B are turned OFF, switches SW3A,Bremain OFF, switches SW4A,B remain OFF, switches SW5A,B remain OFF,switches SW6A,B are turned ON, switch SW7B is turned ON, switch SW8B isturned OFF, switches SW9A,B remain OFF, switches SW10A,B remain OFF,switches SW11A,B are turned OFF, switches SW12A,B are turned OFF, andswitches SW13:16 remain OFF.

During a third amplifying stage, which immediately follows the thirdreset state, the op-amp 200 may operate in the single-ended mode. Themode signal remains high, switches SW1A,B and SW2A,B remain OFF,switches SW3A,B are turned ON, switches SW4A,B are turned ON, switchesSW5A,B remain OFF, switches SW6A,B are turned OFF, switch SW7B remainsON, and switch SW8B remains OFF.

During the fully-differential modes and when the mode signal is low(‘L’), the first mode switch 245 receives a low signal, which turns thefirst mode switch 245 OFF, and the second mode switch 260 receives ahigh signal via the inverter 265, which turns the second mode switch ON.

During the single-ended mode and when the mode signal is high (‘H’), thefirst mode switch 245 receive a high signal, which turns the first modeswitch ON, and the second mode switch 260 receives a low signal via theinverter 265, which turns the second mode switch OFF.

It will be understood by those of ordinary skill in the art that thetransistors may be implemented as either p-channel transistors orn-channel transistors. As such, the operation of the transistors maychange accordingly. For example, the first and second mode switches 245,260 may be implemented as p-channel transistors. In such a case, a highmode signal would turn the switch OFF and a low mode signal would turnthe switch ON.

In the foregoing description, the technology has been described withreference to specific exemplary embodiments. The particularimplementations shown and described are illustrative of the technologyand its best mode and are not intended to otherwise limit the scope ofthe present technology in any way. Indeed, for the sake of brevity,conventional manufacturing, connection, preparation, and otherfunctional aspects of the method and system may not be described indetail. Furthermore, the connecting lines shown in the various figuresare intended to represent exemplary functional relationships and/orsteps between the various elements. Many alternative or additionalfunctional relationships or physical connections may be present in apractical system.

The technology has been described with reference to specific exemplaryembodiments. Various modifications and changes, however, may be madewithout departing from the scope of the present technology. Thedescription and figures are to be regarded in an illustrative manner,rather than a restrictive one and all such modifications are intended tobe included within the scope of the present technology. Accordingly, thescope of the technology should be determined by the generic embodimentsdescribed and their legal equivalents rather than by merely the specificexamples described above. For example, the steps recited in any methodor process embodiment may be executed in any order, unless otherwiseexpressly specified, and are not limited to the explicit order presentedin the specific examples. Additionally, the components and/or elementsrecited in any apparatus embodiment may be assembled or otherwiseoperationally configured in a variety of permutations to producesubstantially the same result as the present technology and areaccordingly not limited to the specific configuration recited in thespecific examples.

Benefits, other advantages and solutions to problems have been describedabove with regard to particular embodiments. Any benefit, advantage,solution to problems or any element that may cause any particularbenefit, advantage or solution to occur or to become more pronounced,however, is not to be construed as a critical, required or essentialfeature or component.

The terms “comprises”, “comprising”, or any variation thereof, areintended to reference a non-exclusive inclusion, such that a process,method, article, composition or apparatus that comprises a list ofelements does not include only those elements recited, but may alsoinclude other elements not expressly listed or inherent to such process,method, article, composition or apparatus. Other combinations and/ormodifications of the above-described structures, arrangements,applications, proportions, elements, materials or components used in thepractice of the present technology, in addition to those notspecifically recited, may be varied or otherwise particularly adapted tospecific environments, manufacturing specifications, design parametersor other operating requirements without departing from the generalprinciples of the same.

The present technology has been described above with reference to anexemplary embodiment. However, changes and modifications may be made tothe exemplary embodiment without departing from the scope of the presenttechnology. These and other changes or modifications are intended to beincluded within the scope of the present technology, as expressed in thefollowing claims.

1. An amplifier circuit, comprising: an operational-amplifiercomprising: a first output terminal; and a second output terminal; aswitching circuit connected to the operational amplifier, wherein theswitching circuit is: selectively operable to generate a variablecapacitance; and selectively connected to the first and second outputterminals; wherein the switching circuit controls a gain-bandwidth ofthe operational amplifier.
 2. The amplifier circuit according to claim1, wherein the switching circuit comprises a plurality of switches and atransistor.
 3. The amplifier circuit according to claim 1, wherein theswitching circuit comprises: a first switch connected in series with atransistor; and a second switch connected in series with the transistor.4. The amplifier circuit according to claim 3, wherein: the first switchis also directly connected to the first output terminal; and the secondswitch is also directly connected to the second output terminal.
 5. Theamplifier circuit according to claim 1, wherein the switching circuitcomprises: a first series-connected circuit comprising: a first switchconnected in series with a first transistor; and a second switchconnected in series with the first transistor; a second series-connectedcircuit comprising: a third switch connected in series with a secondtransistor; and a fourth switch connected in series with the secondtransistor; wherein the first and second series-connected circuits areconnected in parallel with each other.
 6. The amplifier circuitaccording to claim 5, wherein: the first switch is also directlyconnected to the first output terminal; the second switch is alsodirectly connected to the second output terminal; the third switch isalso directly connected to the first output terminal; and the fourthswitch is also directly connected to the second output terminal.
 7. Theamplifier circuit according to claim 1, wherein the operationalamplifier is configured as a dual-mode operational amplifier capable ofoperating as a fully-differential amplifier and a single-endedamplifier.
 8. The amplifier circuit according to claim 1, wherein theoperational amplifier comprises: a first sub-circuit connected to asupply voltage and a bias node, and comprising: a first transistorconnected in series with a second transistor; a third transistorconnected in series with the second transistor; and a first nodepositioned between the second and third transistors; a first mode switchconfigured to selectively connect the first node to the bias node; asecond sub-circuit connected to the first sub-circuit; a thirdsub-circuit connected to: the supply voltage; and the bias node; afourth sub-circuit connected to the supply voltage; and a second modeswitch configured to selectively connect the fourth sub-circuit to thebias node; wherein the operational amplifier operates in afully-differential mode and a single-ended mode according to the firstand second mode switches.
 9. The amplifier circuit according to claim 8,wherein: the first mode switch is responsive to a first mode signal; thesecond mode switch is responsive to a second mode signal; and the secondmode signal is the inverse of the first mode signal.
 10. A method forcontrolling a gain-bandwidth of an operational amplifier, comprising:decreasing the gain-bandwidth comprising: selectively increasing acapacitance at an output terminal of the operational amplifier; andincreasing the gain-bandwidth comprising: selectively decreasing thecapacitance at the output terminal of the operational amplifier.
 11. Themethod according to claim 10, wherein connecting the transistor to theoutput terminal comprises: selectively operating a first switchconnected in series with a first terminal of the transistor; andselectively operating a second switch connected in series with a secondterminal of the transistor.
 12. The method according to claim 10,wherein selectively increasing the capacitance at the output terminalcomprises connecting a transistor to the output terminal of theoperational amplifier.
 13. The method according to claim 10, whereinselectively decreasing the capacitance at the output terminal comprisesdisconnecting a transistor from the output terminal of the operationalamplifier.
 14. A system, comprising: a sensor; and an amplifier circuitconnected to the sensor and comprising: a dual-modeoperational-amplifier configured to operate in a fully-differential modeand a single-ended mode, comprising: a first output terminal; and asecond output terminal; a switching circuit selectively connected to theoperational amplifier and configured to control a gain-bandwidth of theoperational amplifier.
 15. The system according to claim 14, wherein theswitching circuit comprises: a first switch connected: directly to thefirst output terminal; and in series with a transistor; and a secondswitch connected: directly to the second output terminal; and in serieswith the transistor.
 16. The system according to claim 14, wherein theswitching circuit comprises: a first series-connected circuitcomprising: a first switch connected in series with a first transistor;and a second switch connected in series with the first transistor; asecond series-connected circuit comprising: a third switch connected inseries with a second transistor; and a fourth switch connected in serieswith the second transistor; wherein the first and secondseries-connected circuits are connected in parallel with each other. 17.The system according to claim 14, wherein the operational amplifier isconfigured as a dual-mode operational amplifier capable of operating asa fully-differential amplifier and a single-ended amplifier.
 18. Thesystem according to claim 14, a first sub-circuit connected to a supplyvoltage and a bias node, and comprising: a first transistor connected inseries with a second transistor; a third transistor connected in serieswith the second transistor; and a first node positioned between thesecond and third transistors; a first mode switch configured toselectively connect the first node to the bias node; a secondsub-circuit connected to the first sub-circuit; a third sub-circuitconnected to: the supply voltage; and the bias node; a fourthsub-circuit connected to the supply voltage; and a second mode switchconfigured to selectively connect the fourth sub-circuit to the biasnode; wherein the operational amplifier operates in a fully-differentialmode and a single-ended mode according to the first and second modeswitches.
 19. The system according to claim 14, wherein the switchingcircuit is selectively operable to generate a variable capacitance. 20.The system according claim 14, wherein the switching circuit isselectively connected to the first and second output terminals of theoperational amplifier.